Semiconductor photomultiplier

ABSTRACT

The present disclosure relates to a semiconductor photomultiplier comprising a substrate; an array of photosensitive cells formed on the substrate that are operably coupled between an anode and a cathode. A set of primary bus lines are provided each being associated with a corresponding set of photosensitive cells. A secondary bus line is coupled to the set of primary bus lines. An electrical conductor is provided having a plurality of connection sites coupled to respective connection locations on the secondary bus line for providing conduction paths which have lower impedance than the secondary bus line.

RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.14/801,592, filed Jul. 16, 2015, now U.S. Pat. No. 9,659,980, issued May23, 2017, which claims priority from and is a continuation-in-part ofU.S. patent application Ser. No. 14/577,123, filed Dec. 19, 2014, nowabandoned, which applications are incorporated herein in their entirety.Related subject matter is found in a co-pending patent applicationentitled “Semiconductor Photomultiplier”, U.S. patent application Ser.No. 15/335,658, filed Oct. 27, 2016, invented by Brian McGarvey, StephenJohn Bellis and John Carlton Jackson and assigned to the assignee hereof

FIELD OF THE INVENTION

The present disclosure relates to photon detectors. In particular, thepresent disclosure relates to high sensitivity photon detectors such assemiconductor photomultipliers. In particular, but not exclusively, thepresent disclosure relates to semiconductor photomultipliers (SiPMs orSPMs) in such areas as Positron Emission Tomography [PET], includingTime-Of-Flight PET [TOF-PET], Laser Ranging [LIDAR] applications, bioluminescence, High Energy Physics [HEP] detectors.

BACKGROUND

SiPMs are semiconductor photon sensitive devices made up of an array ofvery small Geiger-mode avalanche photodiode (APD) cells on a substratesuch as silicon. APD cells vary in dimension from several micron to 100microns depending on the mask used, and can have a typical density of upto 3000 microcells/sq. mm. Avalanche diodes can also be made from othersemiconductors besides silicon, depending on the properties that aredesirable. Silicon detects in the visible and near infrared range, withlow multiplication noise (excess noise). Germanium (Ge) detects infraredto 1.7 μm wavelength, but has high multiplication noise. InGaAs (IndiumGallium Arsenide) detects to a maximum wavelength of 1.6 μm, and hasless multiplication noise than Ge. InGaAs is generally used for themultiplication region of a heterostructure diode, is compatible withhigh speed telecommunications using optical fibres, and can reach speedsof greater than Gbit/s. Gallium nitride operates with UV light. HgCdTe(Mercury Cadmium Telluride) operates in the infrared, to a maximumwavelength of about 14 μm, requires cooling to reduce dark currents, andcan achieve a very low level of excess noise.

Silicon avalanche diodes can function with breakdown voltages of 100to >1000V, typically. APDs exhibit internal current gain effect of about100-1000 due to impact ionization, or avalanche effect, when a highreverse bias voltage is applied (approximately 100->200 V in silicon,depending on the doping profile in the junction). SiliconPhotomultipliers or SiPMs can achieve a gain of 10⁵ to 10⁶ by usingGeiger mode APDs also known as Single Photon Avalanche Diodes (SPADs)which operate with a reverse voltage that is greater than the breakdownvoltage, and by maintaining the dark count event rate at a sufficientlylow level. The current generated by an avalanche event must be quenchedby an appropriate current limited scheme so that the device can recoverand reset after an avalanche event. SiPM sensors have lower operatingvoltages than APDs and have a breakdown voltage from 10-100 Volts.

Silicon Photomultipliers typically include a matrix of major and minorbus lines. The minor bus lines connect directly to the microcells. Theminor bus lines are then joined to bond pads by a major bus line. Theminor bus lines are loaded with the inductance, capacitance andresistance of the microcells. The major bus lines are then loaded withthe inductance, capacitance and resistance of the minor bus lines. Therise time, delay and recovery time of signal from a microcell on theSiPM will therefore depend strongly on its position in the SiPM. Thevariation in rise time and delay across the array will give rise toincreased jitter and therefore increased coincidence resolving time(CRT) or timing jitter.

There is therefore a need to provide a semiconductor photomultiplierwhich addresses at least some of the drawbacks of the prior art.

SUMMARY

In one aspect, there is provided a semiconductor photomultipliercomprising:

a substrate;

an array of photosensitive elements formed on a first major surface ofthe substrate;

a plurality of primary bus lines interconnecting the photosensitiveelements;

at least one segmented secondary bus line provided on a second majorsurface of the substrate which is operably coupled to one or moreterminals; and

multiple vertical interconnect access (vias) extending through thesubstrate operably coulping the primary bus lines to the at least onesegmented secondary bus line.

In another aspect, the photosensitive element comprises a single photonavalanche diode (SPAD).

In a further aspect, a quench element is associated with each SPAD.Advantageously, the quench element is a passive component resistor.Preferably, the quench element is an active component transistor.

In one aspect, each segment of the segmented secondary bus line has anassociated via coupled to a corresponding primary bus line.

In a further aspect, each photosensitive element is part of a microcell.

In another aspect, at least some of the segments of the segmentedsecondary bus line are of equal length in order to equalise the signaldelays from the microcells to the one or more terminals.

In a further aspect, the length of at least some of the primary buslines are of equal length in order to equalise the signal delays fromthe microcells to the one or more terminals.

In one aspect, each microcell comprises a photodiode. Advantageously,each microcell comprises a resistor coupled in series to the photodiode.Preferably, a capacitive element is provided.

In another aspect, the interconnected photosensitive elements arearranged in a grid configuration.

In a further aspect, the primary buses lines are parallel to columns inthe grid configuration. Advantageously, at least some of the primary buslines extend between the columns.

In another aspect, the primary and secondary bus lines are perpendicularto each other. Advantageously, each photosensitive element comprises anavalanche photodiode or a single photon avalanche diode.

In one aspect, each interconnected photosensitive element comprises aquench resistor coupled in series to the avalanche photodiode or asingle photon avalanche diode.

The present disclosure relates to a substrate comprising:

an array of photosensitive elements formed on a first major surface ofthe substrate;

a plurality of primary bus lines interconnecting the photosensitiveelements;

at least one segmented secondary bus line provided on a second majorsurface of the substrate which is operably coupled to one or moreterminals; and

multiple vertical interconnect access (vias) extending through thesubstrate operably coulping the primary bus lines to the at least onesegmented secondary bus line.

The present disclosure also relates to a method of fabricating asemiconductor photomultiplier; the method comprising:

forming an array of photosensitive elements on a first major surface ofa substrate;

providing a plurality of primary bus lines interconnecting thephotosensitive elements;

providing at least one segmented secondary bus line on a second majorsurface of the substrate which is operably coupled to one or moreterminals; and

providing multiple vertical interconnect access (vias) extending throughthe substrate operably coulping the primary bus lines to the at leastone segmented secondary bus line.

The present disclosure also relates to a semiconductor photomultipliercomprising:

a substrate;

an array of photosensitive cells formed on the substrate that areoperably coupled between an anode and a cathode;

a set of primary bus lines each being associated with a correspondingset of photosensitive cells;

a secondary bus line coupled to the set of primary bus lines;

an electrical conductor having a plurality of connection sites coupledto respective connection locations on the secondary bus line forproviding conduction paths which have lower impedance than the secondarybus line.

In one aspect, the array of photosensitive cells are formed on a firstmajor surface of the substrate.

In another aspect, the secondary bus line is provided on the first majorsurface of the substrate. In one aspect, the electrical conductor isprovided on a second major surface of the substrate which is oppositethe first major surface.

In one aspect, interconnects extend between the connection sites and theconnection locations. Advantageously, each connection site has anassociated connection location which are wire bonded together. In oneexample, the respective connection sites are uniformly spaced apart. Inanother exemplary arrangement, the respective connection locations areuniformly spaced apart.

In a further aspect, the electrical conductor is provided as an outputlead on a leadframe. Advantageously, the leadframe includes a cathodelead and an anode lead. In one exemplary arrangement, the output leadincludes a plurality of fingers each defining a corresponding connectionsite. In one example, each finger is associated with a corresponding oneof the connection locations on the secondary bus line. Advantageously,each connection location on the secondary bus line has an associatedlanding pad for receiving a wire bond.

In one aspect, the electrical conductor comprises a metal track.Advantageously, the electrical conductor is provided on a carriersubstrate. In exemplary arrangements, the carrier substrate comprisesone of a leadframe, a PCB, a ceramic chip carrier, and a pre-molded chipcarrier.

In a further aspect, the array of photosensitive cells are arranged in agrid configuration. Advantageously, at least some of the primary buslines extend between the columns of the grid configuration. In oneexample, the primary bus lines are parallel to one another.

In one aspect, the photosensitive cell comprises a single photonavalanche diode (SPAD). Advantageously, a quench element is associatedwith each SPAD. In one example, the quench element is a passivecomponent resistor. In another example, the quench element is an activecircuit of component transistors.

In an exemplary arrangement each photosensitive cell comprises aphotodiode. Advantageously, each photosensitive cell comprises aresistor coupled in series to the photodiode. In one example, eachphotosensitive cell comprises a capacitive element.

In another exemplary arrangement, each photosensitive cell comprises anavalanche photodiode or a single photon avalanche diode.

In one aspect, a heat sink is provided. In an exemplary arrangement, theheat sink is co-operable with the substrate. In one example, the heatsink is co-operable with the electrical conductor.

In one aspect, the substrate is provided on a first wafer. In oneexemplary arrangement, the first wafer is operably coupled to a secondwafer. Advantageously, the first wafer and the second wafer are instacked arrangement. In one example, the first and second wafers areparallel to one another. In one arrangement, circuit components areprovided on the second wafer. In one aspect, the first and second wafersare operably coupled together with a solder bump interconnectionarrangement.

In another aspect, the connection sites of the electrical conductor arecoupled to connection locations on the secondary bus without usingthrough-silicon vias in order to maximise the area on the substrateavailable for accommodating photosensitive active areas.

The present disclosure also relates to a semiconductor photomultipliercomprising:

a substrate;

an array of photosensitive cells formed on the substrate that areoperably coupled between an anode and a cathode;

a first set of primary bus lines and a second set of primary bus lineseach being associated with a corresponding set of photosensitive cells;

a first secondary bus line coupled to the first set of primary buslines;

a second secondary bus line coupled to the second set of primary buslines;

a first electrical conductor having a plurality of connection sitescoupled to respective connection locations on the first secondary busline for providing conduction paths which have lower impedance than thefirst secondary bus line; and

a second electrical conductor having a plurality of connection sitescoupled to respective connection locations on the second secondary busline for providing conduction paths which have lower impedance than thesecond secondary bus line.

In one aspect, the first set of primary bus lines are capacitivelycoupled to the photosensitive cells. In another exemplary arrangement,the second set of primary bus lines are capacitively coupled to thephotosensitive cells.

Additionally, the present disclosure relates to a semiconductorphotomultiplier and readout system comprising:

an array of photosensitive cells operably coupled between an anode and acathode;

a set of primary bus lines each being associated with a correspondingset of photosensitive cells;

a secondary bus line coupled to the set of primary bus lines;

an electrical conductor having a plurality of connection sites coupledto respective connection locations on the secondary bus line forproviding conduction paths which have lower impedance than the secondarybus line; and

a readout circuit operable for communicating with the electricalconductor.

Furthermore, the present disclosure relates to a semiconductorphotomultiplier and a readout system comprising:

an array of photosensitive cells that are operably coupled between ananode and a cathode;

a first set of primary bus lines and a second set of primary bus lineseach being associated with a corresponding set of photosensitive cells;

a first secondary bus line coupled to the first set of primary buslines;

a second secondary bus line coupled to the second set of primary buslines;

a first electrical conductor having a plurality of connection sitescoupled to respective connection locations on the first secondary busline for providing conduction paths which have lower impedance than thefirst secondary bus line;

a second electrical conductor having a plurality of connection sitescoupled to respective connection locations on the second secondary busline for providing conduction paths which have lower impedance than thesecond secondary bus line; and

a readout circuit operable for communicating with the first and secondelectrical conductors.

The present disclosure also relates to a method of fabricating asemiconductor photomultiplier; the method comprising:

providing an array of photosensitive cells on a substrate that areoperably coupled between an anode and a cathode;

providing a set of primary bus lines each being associated with acorresponding set of photosensitive cells;

providing a secondary bus line coupled to the set of primary bus lines;and

providing an electrical conductor having a plurality of connection sitescoupled to respective connection locations on the secondary bus line forproviding conduction paths which have lower impedance than the secondarybus line.

Additionally, the present teaching is directed to a method offabricating a semiconductor photomultiplier comprising:

providing an array of photosensitive cells on a substrate that areoperably coupled between an anode and a cathode;

providing a first set of primary bus lines and a second set of primarybus lines each being associated with a corresponding set ofphotosensitive cells;

providing a first secondary bus line coupled to the first set of primarybus lines;

providing a second secondary bus line coupled to the second set ofprimary bus lines;

providing a first electrical conductor having a plurality of connectionsites coupled to respective connection locations on the first secondarybus line for providing conduction paths which have lower impedance thanthe first secondary bus line; and

providing a second electrical conductor having a plurality of connectionsites coupled to respective connection locations on the second secondarybus line for providing conduction paths which have lower impedance thanthe second secondary bus line.

These and other features will be better understood with reference to thefollowings Figures which are provided to assist in an understanding ofthe present teaching.

BRIEF DESCRIPTION OF THE DRAWINGS

The present teaching will now be described with reference to theaccompanying drawings in which:

FIG. 1 illustrates an exemplary structure of a silicon photomultiplier.

FIG. 2 is a schematic circuit diagram of an exemplary siliconphotomultiplier.

FIG. 3 is a schematic circuit diagram of an exemplary siliconphotomultiplier.

FIG. 4 is a top plan view of an exemplary silicon photomultiplier.

FIG. 5 is a diagrammatic view of four microcells.

FIG. 6A is a graph showing that signal delay, rise time and overallshape depend on the position of the microcell.

FIG. 6B is a graph showing the improvement in relation to signal delayand signal uniformity as result of using a segmented secondary (major)bus line in accordance with the present disclosure.

FIG. 7 is a graph showing that signal delay, rise time and overall shapedepend on the position of the microcell.

FIG. 8 is a graph which shows the signal from the microcells furthestfrom the major row (furthest from terminal) compared with the signalfrom those closest to it.

FIG. 9 shows a cross sectional view of a photomultiplier in accordancewith the present teaching.

FIG. 10 is a plan view of a bottom surface of the photomultiplier ofFIG. 9.

FIG. 11 is a simulated graph of the signals on a segmented (major) busline on the bottom surface of the photomultiplier of FIG. 9.

FIG. 12 is a diagrammatic illustration of primary (minor) and secondary(major) bus lines of the photomultiplier in accordance with the presentteaching.

FIG. 13 is a plan view of a bottom surface of the photomultiplier inaccordance with the present teaching.

FIG. 14 is a diagrammatic illustration of primary and secondary buslines of the photomultiplier in accordance with the present teaching.

FIG. 15 is a graph illustrating improvement in delay time as result ofincreasing the number of segments.

FIG. 16 is a diagrammatic illustration of an exemplary photomultiplier.

FIG. 17 is a diagrammatic illustration of an exemplary photomultiplier.

FIG. 18 is an diagrammatic illustration of a lead frame.

FIG. 19 is a top plan perspective view of an exemplary photomultiplierof FIG. 17.

FIG. 20 is bottom plan perspective view of the photomultiplier of FIG.17.

FIG. 21 is a diagrammatic illustration of an exemplary semiconductorphotomultiplier showing the layout of the primary and secondary buslines.

FIG. 22 is a graph showing improved performance as a result ofincorporating a heat sink.

FIG. 23 is a side perspective view of an exemplary photomultiplier.

DETAILED DESCRIPTION OF THE DRAWINGS

The present disclosure will now be described with reference to someexemplary semiconductor photomultipliers. It will be understood that theexemplary semiconductor photomultipliers are provided to assist in anunderstanding of the teaching and is not to be construed as limiting inany fashion. Furthermore, circuit elements or components that aredescribed with reference to any one Figure may be interchanged withthose of other Figures or other equivalent circuit elements withoutdeparting from the spirit of the present teaching. It will beappreciated that for simplicity and clarity of illustration, whereconsidered appropriate, reference numerals may be repeated among thefigures to indicate corresponding or analogous elements.

Referring initially to FIG. 1, a silicon photomultiplier 100 comprisingan array of Geiger mode photodiodes is shown. The array is formed on asemiconductor substrate 150 using semiconductor processes which will beknown to one skilled in the art and may include for example, but notlimited to, deposition, implantation, diffusion, patterning, doping, andetching. Patterned layers of conducting material, insulating materialand doped areas of semiconductor form the structure of the photodiode. Aquench resistor is provided adjacent to each photodiode which may beused to limit the avalanche current. The photodiodes are electricallyconnected to common biasing and ground electrodes by aluminium orsimilar conductive tracking.

The Silicon Photomultiplier 100 integrates a dense array of small,electrically and optically isolated Geigermode photodiodes 115. Eachphotodiode 115 is coupled in series to a quench resistor 120. Eachphotodiode 115 and its associated quench resistor 120 are referred to asa microcell 125. The number of microcells 125 typically number between100 and 3000 per mm². The signals of all microcells 125 are then summedto form the output of the SiPM 100. A simplified electrical circuit 130is provided to illustrate the concept in FIG. 2. Each microcell 125detects photons identically and independently. The sum of the dischargecurrents from each of these individual binary detectors combines to forma quasi-analog output, and is thus capable of giving information on themagnitude of an incident photon flux.

Each microcell 125 generates a highly uniform and quantized amount ofcharge every time the microcell 125 undergoes a Geiger breakdown. Thegain of a microcell 125 (and hence the detector) is defined as the ratioof the output charge to the charge on an electron. The output charge canbe calculated from the over-voltage and the microcell capacitance.

$G = \frac{{C \cdot \Delta}\; V}{q}$

Where:

G is the gain of the microcell;

C is the capacitance of the microcell;

ΔV is the over-voltage; and

q is the charge of an electron.

Referring now to FIG. 3 which illustrates a silicon photomultiplier 300described in PCT Patent Application no. WO 2011/117309 of which thepresent assignee is the applicant, the contents are incorporated hereinby reference. The SPM 300 has a third electrode 305 which iscapacitively coupled to each photodiode cathode 310 in order to providea fast readout of the avalanche signals from the photodiodes 315. Whenthe photodiode 315 emits a current pulse, part of the resulting changein voltage at the cathode 310 will be coupled via mutual capacitance 320into the third (fast) electrode 305. Using the third electrode 305 forreadout avoids the compromised transient performance resulting from therelatively large RC time constant associated with the biasing circuit.

It will be appreciated by those skilled in the art that siliconphotomultipliers comprise major (secondary) bus lines 440 and minor(primary) bus lines 450 as illustrated in FIG. 4. In siliconphotomultipliers know heretofore the minor bus lines 450 connectdirectly to the microcells 125. The minor bus lines 450 are then coupledto major bus line 440 which connect to the bond pads associated with theterminals 370 and 305. Typically, the minor bus lines 450 extendvertically between the columns of microcells 125; while the major buslines 440 extend horizontally adjacent the outer row of the microcells125. The minor bus lines 450 are loaded with the inductance, capacitanceand resistance of the microcells 125. The major bus lines 440 are thenloaded with the inductance, capacitance and resistance of the minor buslines 450. The rise time, delay and recovery time of signal from amicrocell 125 on the SiPM will therefore depend significantly on itsposition in the SiPM. The variation in rise time and delay across thearray will give rise to increased jitter and therefore increasedcoincidence resolving time (CRT). It will be appreciated by thoseskilled in the art that a microcell 125 firing at position A will have avery different signal path to microcell 125 firing at position B. Therise time and delay of the signal will be different as the signal pathis not uniform. The range of these parameters impacts coincidenceresolving time (CRT) significantly.

Referring now to FIGS. 5 to 7, which shows experimental data to quantifythe range of delays and rise times seen across a SiPM. Pulses comingfrom different areas of the SiPM were compared by partially (85%)blacking out areas as indicated by labels a, b, c, and d in FIG. 5.

-   -   a) The minor rows closest to the anode were exposed. The signal        path along the major row is short.    -   b) The minor rows at the end of the major rows were exposed.        This is the opposite of (a). The signal path along the major row        will be long.    -   c) The microcells on the minor bus closest to the major bus are        exposed. The signal path along the minor rows will be short.    -   d) The micro cells on the minor bus furthest from the major row        are exposed. The signal path along the minor rows will be long.

It is clear from the graphs in FIGS. 6A, 6B and 7 that the standardterminal 370 and fast output terminal 305 signal delay, rise time andoverall shape depend strongly on position on the major row. FIG. 6Aillustrates the signals measured at the standard terminal 370, whileFIG. 7 illustrates the signals measured at the fast terminal 305. Thedelay from difference between ‘a’ and ‘b’ is approximately 400 ps. FIG.6B is a graph showing the improvement in relation to signal delay andsignal uniformity as result of using a segmented secondary bus line inaccordance with the present teaching. In the exemplary arrangement thedelay Δt was reduced to approximately 25 ps at 25 mV. An additionaladvantage of the segmented secondary bus approach results in greateruniformity in signal height which will further improve CRT and enable awider range of threshold voltage selection to be used during an analogueto digital conversion.

The graph of FIG. 8 shows the signal from fourtheen microcells furthestfrom the major row (anode terminal) compared with the signal fromfourtheen microcells closest to major row (anode terminal). It is clearthat there is significant time delay between the two signals. It isdesirable to segment the major bus line in order to reduce the load onthe signal. If the segments were joined together on top of the substrate150, the area taken up by the additional bus lines would be subtractedfrom the optically active area, significantly reducing thephoto-detection efficiency (PDE).

Referring now to FIGS. 9 and 10 which illustrates an exemplary layout ofminor bus lines 950 and major bus lines 940 in accordance with thepresent teaching. The minor bus lines 950 extend vertically between thecolumns of microcells 125 similar as previously described with referenceto FIG. 4. The major bus lines 940 are provided on a lower surface 960of the substrate 150 and are operably coupled to the minor bus lines 950via true silicon vias (TSVs) 970. The minor bus lines 950 interconnectthe microcells 125 which are formed on an upper surface 965 of thesubstrate 150. The TSVs 970 are vertical connections which passcompletely through the substrate 150. The number of major bus lines 940which may be used is significantly increased compared to the arrangementof FIG. 4 because the area for accommodating the major bus lines 940 isnot limited to the periphery of the upper major surface of the substrate150. The full area of the bottom surface 960 of the substrate 150 isavailable to accommodate the major bus lines 940. The major bus line 940is segmented into multiple segments 980 as illustrated in FIG. 10. Inthe exemplary embodiment, six segments 980 extend horizontally on thebottom surface 960 of the substrate 150. It is will be appreciated bythose skilled in the art that the major bus line 940 may be segmentedinto any desirable number of segments 980. Routing the major bus lines940 under the silicon substrate 150 minimises the impact on theoptically active area of the SiPM. It will be clear to those skilled inthe art that CRT is strongly dependant on the range of delay seen acrossthe array of microcells in the SiPM. Reducing the range of delay bysegmenting the major bus lines 940 will reduce CRT.

Referring now to the graph of FIG. 11 which is a simulated graph of theSiPM of FIG. 10 showing the signal delay, rise time and overall shape ofthe signal of four different segments connected to different major buslengths (980). The signal delay between the fastest and slowest signalis approximately 150 ps. Thus making the major bus lengths equal underthe silicon will reduce the delay range further, thereby reducing CRT.Such a scheme is illustrated in FIG. 13.

Referring now to FIG. 12 which shows TSVs positioned along the major rowassociated with the standard terminal 370 and TSVs positioned along themajor row associated with the fast terminal 305. Using TSVs allows thearrays of microcells 125 on top surface 965 of the substrate 150 to besegmented so that the major rows are shorted. The major and minor rowsmay be connected to the under side of the substrate at various positionsin the area of the die and shorted via copper tracks. This willeffectively reduce the load on each segment of microcells 125. Thereduced load will lead to a reduced range of delays (jitter and CRT).Further reductions in jitter can be achieved by using minor rows ofvarious lengths so that the minor row load seen by a microcell furthestfrom the terminal is smallest and that seen by a microcell closes to theterminal is largest.

Referring now to FIG. 13 there illustrated a segmented major bus line onthe bottom surface 960 of the substrate 150. The major bus line issimilar to the arrangement described in FIG. 10 with the exception thattrack length is increased in order to equalise the signal delays fromthe microcells 125 to the terminals. This is possible because due to theextra space under the substrate 150 to route the metal lines.

Referring now to FIG. 14 there is illustrated an exemplary arrangementof the minor bus lines where the signal paths from the microcells to theterminals are equalised. For example, the signal path from position A tothe terminal is approximately equal to signal path from position B. Sucha scheme can be incorporated with the arrangement illustrated in FIGS.9, 10, 12, 13 in order to further reduce the delay range.

The graph of FIG. 15 shows that the rate of improvement in delay time Δtwith increasing the number of segments. In particular, the delay issignificantly reduced when the secondary bus line includes five or moresegments. Furthermore, by splitting the primary bus into a first set ofbus lines 990 and a second set of bus lines 992 as illustrated in FIG.16 has a significant impact on signal delay time Δt. However furtherdividing primary bus line has a less significant impact on Δtperformance. It has been found through experimentation that the optimumnumber of TSVs for a 6 mm SiPM is six on the secondary bus line with theprimary bus lines divided into two. It will be appreciated by thoseskilled in the art that signal delays are reduced by increasing thenumber TSVs. The area taken up by the additional TSVs is subtracted fromthe optically active area, thus reducing the photo-detection efficiency(PDE). Through experimentation it has been found that there is a 0.05%reduction of PDE for each additional TSV which are included. Thepresenting teaching optimises Δt while minimising the trade off by thereduction in PDE.

Referring now to FIGS. 17 to 20, there is provided another semiconductorphotomultiplier 1000. The semiconductor photomultiplier 1000 is similarto the photomultipiers which have been previously described with themain difference being that TSVs are not used. The semiconductorphotomultiplier 1000 comprises a substrate 1005; an array ofphotosensitive cells 1010 formed on the substrate 1005. The schematiccircuit diagram of the photosensitive cell 1010 substantiallycorresponds to the schematic of FIG. 3 and like elements are referencedby similar numerals for convenience. The SPM 1000 has a third electrode305 which is capacitively coupled to each photodiode cathode 310 inorder to provide a fast readout of the avalanche signals from thephotodiodes 315. When the photodiode 315 emits a current pulse, part ofthe resulting change in voltage at the cathode 310 will be coupled viamutual capacitance 320 into the third (fast) electrode 305. Using thethird electrode 305 for readout avoids the compromised transientperformance resulting from the relatively large RC time constantassociated with the biasing circuit. Each photosensitive cell 1010 isassociated with an output node for facilitating reading the outputsignal from each cell 1010. The photosensitive cells 1010 are arrangedin a grid configuration having rows and columns. A plurality of primarybuses 1020 are provided for interconnecting the output nodes of thephotosensitive cells 1010 of a corresponding column. An electricalconductor 1025, best illustrated in FIG. 18, is provided having aplurality of connection sites 1030 for facilitating interconnecting therespective connection sites 1030 to the corresponding connectionlocations on the secondary bus 1015 for providing conduction paths whichhave lower impedance than the secondary bus line 1015. This willeffectively reduce the load on each segment of the photosensitive cells.The reduced load will lead to a reduced range of delays (jitter andCRT). The grid formation is provided on a top major surface of thesubstrate 1005 as best illustrated in FIG. 19.

In the exemplary arrangement the array of photosensitive cells 1010 areoperably coupled between an anode and a cathode. A set of primary buslines 1020 are provided which are each associated with a correspondingset of photosensitive cells 1010. For example, each primary bus line1020 is associated with the photosensitive cells of a particular column.A secondary bus line 1015 is coupled to the set of primary bus lines1020. The electrical conductor 1025 includes a plurality of connectionsites 1030 which are coupled to respective connection locations on thesecondary bus line 1015 for providing conduction paths which have lowerimpedance than the secondary bus line.

In the exemplary embodiment the array of photosensitive cells 1010 areformed on a first major surface 1012 of the substrate 1005. Thesecondary bus line 1015 is also provided on the first major surface ofthe substrate 1005 and is operably coupled to the primary bus lines1020. Wire bonds extend between the connection sites on the electricalconductor 1025 and the connection locations on the secondary bus line1015 such that each connection site is associated with a correspondingconnection location. Each connection location on the secondary bus hasan associated landing pad 1026 for receiving a wire bond. In oneexemplary arrangement, the respective connection sites are uniformlyspaced apart. Similarly, the respective connection locations may also beuniformly spaced apart.

The electrical conductor 1025 may be provided as an output lead 1035 ona leadframe, for example. In a preferred arrangement the leadframe islocated on a bottom major surface of the substrate 1005 as bestillustrated in FIG. 19. The output lead 1035 includes a plurality offingers 1045 each defining a corresponding connection site. The numberof fingers 1045 corresponds to the number of connection locations on thesecondary bus 1015. Interconnects in the form of wire bonds extendbetween the fingers and the connection locations. The leadframe may alsoinclude a cathode lead 1055 and an anode lead 1060. The substrate 1005and portions of the leads are encapsulated in an encapsulating materialwhich defines a housing. The distal portions of the leads extend throughthe housing for facilitating electrical coupling the circuit of the SPMto other circuit elements. It is not intended to limit the presentteaching to a leadframe as other alternative mechanisms such as metaltracking on a PCB or similar carrier substrate may be used. Similarcarrier substrates may include, for example but not limited to, ceramicchip carriers, pre-molded chip carriers, direct bonding to another wafereither via TSV or on the top surface for back illuminated operation.

The array of photosensitive cells are arranged in a grid configurationwith at least some of the primary bus lines extending between thecolumns of the grid configuration. The primary bus lines are typicallyparallel to one another but other configurations are possible. Thephotosensitive cell 1010 may comprises an avalanche photodiode or asingle photon avalanche diode and an associated quench element. Thequench element may be a passive component resistor. Alternatively, thequench element may include an active circuit of component transistors.

The connection sites of the electrical conductor are coupled toconnection locations on the secondary bus without using through-siliconvias in order to maximise the area on the substrate available foraccommodating photosensitive active areas. If TSV were used each TSV mayresult in a loss of approximately 0.05% active area which directlyreduces PDE. The electrical conductor arrangement with a plurality ofconnection sites coupled to respective connection locations on thesecondary bus line using wire bonds minimises PDE loss whilstsignificantly improving signal delay performance.

The layout of the primary bus lines 1020, the secondary bus line 1015and the electrical conductor 1025 allows the photosensitive cells 1010to comprises the circuit of FIG. 3, for example, as best illustrated inFIG. 21. In this way, the photomultiplier 1000 may include an array ofphotosensitive cells 1010 that are operably coupled between an anode anda cathode. A first set of primary bus lines 1020A and a second set ofprimary bus lines 1020B are each associated with a corresponding set ofphotosensitive cells 1010. A first secondary bus line 1015A is coupledto the first set of primary bus lines 1020A. A second secondary bus line1015B is coupled to the second set of primary bus lines 1020B. A firstelectrical conductor is provided having a plurality of connection sitescoupled to respective connection locations on the first secondary busline 1020A for providing conduction paths which have lower impedancethan the first secondary bus line 1020A. A second electrical conductoris provided having a plurality of connection sites coupled to respectiveconnection locations on the second secondary bus line 1020B forproviding conduction paths which have lower impedance than the secondsecondary bus line 1020B. The first set of primary bus lines 1015A maybe capacitively coupled to the photosensitive cells 1010. The second setof primary bus lines 1015B may be capacitively coupled to thephotosensitive cells. A readout circuit may be provided forcommunicating with the first and second electrical conductors.

A heat sink 1050 optionally may be provided to further enhance theperformance of the semiconductor photomultiplier 1000. Thephotomultiplier 1000 becomes less effective after a second breakdownvoltage point is reached as illustrated in FIG. 22. It will beappreciated by those skilled in the art that the second breakdown onsetvoltage is temperature dependant. Advantageously, the second breakdownonset voltage may be increased by incorporating a heat sink which coolsthe photomultiplier 1000 by dissipating heat into the surrounding area.As a consequence, the operating voltage range of the SiPM may beincreased.

Referring now to FIG. 23 which describes an optional arrangement wherebythe substrate is provided on a first wafer 1080. The first wafer 1080 isoperably coupled to a second wafer 1085 in a stacked arrangement withboth wafers substantially parallel to one another. The second wafer 1085may include circuit components such as a readout circuit by way ofexample. In the stacked arrangement, the first and second wafers areoperably coupled together with a solder bump interconnection arrangement1090.

It will be appreciated by those of ordinary skill in the art that thesilicon photomultiplier of the present teaching may be fabricated on thesubstrate 1005 using conventional semiconductor processing techniquesand may include for example, but not limited to, deposition,implantation, diffusion, patterning, doping, and etching. In this way,the method of fabrication may include the following steps which areprovided by way of example; providing an array of photosensitive cellson a substrate that are operably coupled between an anode and a cathode;providing a set of primary bus lines each being associated with acorresponding set of photosensitive cells; providing a secondary busline coupled to the set of primary bus lines; and providing anelectrical conductor having a plurality of connection sites coupled torespective connection locations on the secondary bus line for providingconduction paths which have lower impedance than the secondary bus line.

In an alternative embodiment, the fabrication steps may include by wayof example; providing an array of photosensitive cells on a substratethat are operably coupled between an anode and a cathode; providing afirst set of primary bus lines and a second set of primary bus lineseach being associated with a corresponding set of photosensitive cells;providing a first secondary bus line coupled to the first set of primarybus lines; providing a second secondary bus line coupled to the secondset of primary bus lines; providing a first electrical conductor havinga plurality of connection sites coupled to respective connectionlocations on the first secondary bus line for providing conduction pathswhich have lower impedance than the first secondary bus line; andproviding a second electrical conductor having a plurality of connectionsites coupled to respective connection locations on the second secondarybus line for providing conduction paths which have lower impedance thanthe second secondary bus line.

It will be appreciated by the person of skill in the art that variousmodifications may be made to the above described embodiments withoutdeparting from the scope of the present invention. In this way it willbe understood that the teaching is to be limited only insofar as isdeemed necessary in the light of the appended claims. The termsemiconductor photomultiplier is intended to cover any solid statephotomultiplier device such as Silicon Photomultiplier [SiPM],MicroPixel Photon Counters [MPPC], MicroPixel Avalanche Photodiodes[MAPD] but not limited to.

Similarly the words comprises/comprising when used in the specificationare used to specify the presence of stated features, integers, steps orcomponents but do not preclude the presence or addition of one or moreadditional features, integers, steps, components or groups thereof.

We claim:
 1. A readout system comprising: an array of photosensitivecells operably coupled between an anode and a cathode; a set of primarybus lines each being associated with a corresponding set ofphotosensitive cells of the array of photosensitive cells; a secondarybus line coupled to bus lines of the set of primary bus lines, thesecondary bus line having a plurality of connection locations thereon;an electrical conductor having a plurality of connection sites thereon,each connection site of the plurality of connection sites coupled to arespective connection location of the plurality of connection locationson the secondary bus line; a plurality of interconnects that extendbetween the plurality of connection sites and their correspondingrespective connection locations, wherein each interconnect of theplurality of interconnects defines a corresponding conduction pathbetween the secondary bus line and the electrical conductor; and areadout circuit operable for communicating with the electricalconductor.
 2. The readout system of claim 1, wherein the array ofphotosensitive cells are formed on a first major surface of a substrate.3. The readout system of claim 2, wherein the secondary bus line isprovided on the first major surface of the substrate.
 4. The readoutsystem of claim 3, wherein the electrical conductor is provided on asecond major surface of the substrate, with the second major surfacebeing opposite the first major surface.
 5. The readout system of claim1, wherein each connection site is coupled to its respective connectionlocation by wire bonding.
 6. The readout system of claim 1, whereinconnection sites of the plurality of connection sites are uniformlyspaced apart.
 7. The readout system of claim 6, wherein the respectiveconnection locations are uniformly spaced apart.
 8. The readout systemof claim 1, wherein the electrical conductor is an output lead on aleadframe.
 9. The readout system of claim 8, wherein the leadframeincludes a cathode lead and an anode lead.
 10. The readout system ofclaim 9, wherein the output lead includes a plurality of fingers eachdefining a corresponding connection site of the plurality of connectionsites.
 11. The readout system of claim 10, wherein each finger isassociated with a corresponding one of the plurality of connectionlocations on the secondary bus line.
 12. The readout system of claim 1,wherein each of the plurality of connection locations on the secondarybus line has an associated landing pad for receiving a wire bond. 13.The readout system of claim 1, wherein the electrical conductorcomprises a metal track.
 14. The readout system of claim 1, wherein theelectrical conductor is on a carrier substrate.
 15. The readout systemof claim 14, wherein the carrier substrate comprises one of a PCB, aceramic chip carrier, and a pre-molded chip carrier.
 16. The readoutsystem of claim 1, wherein the array of photosensitive cells is arrangedin a grid configuration having rows and columns.
 17. The readout systemof claim 16, wherein at least some primary bus lines of the set ofprimary bus lines extend between the columns of the grid configuration.18. The readout system of claim 17, wherein the at least some primarybus lines are parallel to one another.
 19. The readout system of claim1, wherein each photosensitive cell of the array of photosensitive cellcomprises a single photon avalanche diode (SPAD).
 20. The readout systemof claim 19, wherein a quench element is associated with each SPAD. 21.The readout system of claim 20, wherein the quench element is a passivecomponent resistor.
 22. The readout system of claim 1, wherein eachphotosensitive cell of the array of photosensitive cell comprises aphotodiode.
 23. The readout system of claim 22, wherein eachphotosensitive cell of the array of photosensitive cell furthercomprises a resistor coupled in series to the photodiode.
 24. Thereadout system of claim 23, wherein each photosensitive cell of thearray of photosensitive cell comprises a capacitive element.
 25. Thereadout system of claim 1, wherein each photosensitive cell of the arrayof photosensitive cell comprises an avalanche photodiode.
 26. Thereadout system of claim 1, further comprising a heat sink that isco-operable with a substrate.
 27. The readout system of claim 1, whereina substrate is provided on a first wafer.
 28. The readout system ofclaim 27, wherein the first wafer is operably coupled to a second wafer.29. The readout system of claim 28, wherein the first wafer and thesecond wafer are in stacked arrangement.
 30. The readout system of claim28, wherein the first wafer and the second wafer are parallel to eachanother.
 31. The readout system of claim 28, wherein circuit componentsare provided on the second wafer.
 32. The readout system of claim 31,wherein the first wafer and the second wafer are operably coupledtogether with a solder bump interconnection arrangement.
 33. The readoutsystem of claim 1, wherein each connection site of the plurality ofconnection sites is coupled to its respective connection location on thesecondary bus line without using through-silicon vias, therebymaximising an area on a substrate available for accommodatingphotosensitive active areas.
 34. A readout system comprising: an arrayof photosensitive cells formed on a substrate that are operably coupledbetween an anode and a cathode; a first set of primary bus lines and asecond set of primary bus lines, wherein each primary bus line of thefirst set of primary bus lines or the second set of primary bus lines isassociated with a corresponding set of photosensitive cells of the arrayof photosensitive cells; a first secondary bus line coupled to the firstset of primary bus lines, the first secondary bus line having a firstplurality of connection locations thereon; a second secondary bus linecoupled to the second set of primary bus lines, the second secondary busline having a second plurality of connection locations thereon; a firstelectrical conductor having a first plurality of connection sitesthereon, each connection site of the first plurality of connection sitescoupled to a respective connection location of the first plurality ofconnection locations on the first secondary bus line for providing afirst plurality of conduction paths between the first secondary bus lineand the first electrical conductor; a second electrical conductor havinga second plurality of connection sites thereon, each connection site ofthe second plurality of connection sites coupled to a respectiveconnection location of the second plurality of connection locations onthe second secondary bus line for providing a second plurality ofconduction paths between the second secondary bus line and the secondelectrical conductor; and a readout circuit operable for communicatingwith the first and second electrical conductors.